Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65 nm strained Si/low-k CMOS tchnology, P. Morrow, C. M. Park, S. Ramanathan, M. Kobrinsky and M. Harmes, IEEE Electron Device Letters, 27, 335 (2006)
https://shriram-ramanathan.org/wp-content/uploads/2025/08/RNBSE_H_RED_RGB-300x61.png00adminhttps://shriram-ramanathan.org/wp-content/uploads/2025/08/RNBSE_H_RED_RGB-300x61.pngadmin2006-08-26 08:38:392020-08-01 17:51:34Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65 nm strained Si/low-k CMOS tchnology, P. Morrow, C. M. Park, S. Ramanathan, M. Kobrinsky and M. Harmes, IEEE Electron Device Letters, 27, 335 (2006)
